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Fiesta® CSGT Synthesis Script Generation Tool

 Benefits
 Key Features
 Specifications
 Environment

Fiesta® CSGT is an ASIC/FPGA synthesis script generation tool targeting Synopsys® synthesis tools. CSGT provides an intuitive graphical user interface, so that the user need not remember and use the synthesis tool commands.

Fiesta® CSGT automates creation of synthesis scripts. The tool reads a set of existing hierarchical Verilog® design files. Design attributes like clocks, port signals are automatically inferred and need not be specified by the user. The user is prompted for the relevant constraints. The tool can generate synthesis scripts for the entire design or for selected modules.

Benefits
  • Intuitive Graphical User Interface promotes easy adoption and integration into design cycle
  • Includes a design hierarchy browser
  • Automatically infers clocks and other port characteristics
  • Saves the project files for reuse
  • User does not need to remember all the design compiler commands and options
  • Forms ask all relevant constraint questions, reducing constraint omissions
  • Automatic generation of scripts for Synopsys Design Compiler.
Key Features
  • Intuitive Graphical User Interface
  • Web based tool
  • Reads existing hierarchical Verilog designs
  • Detects system clocks and ports
  • Provides complete design setup and compile options constraints
  • Generates script for all the modules in the design
  • Selective script generation

Specifications

Inputs
  • Verilog design files
  • GUI based options and constraints
  • Text constraint file
Outputs
  • Scripts for Synopsys Design Compiler tool

Environment
  • Platform independent
  • Web browsers supporting JDK1.3


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