Devices supported in the Program
The program covers these following Actel devices with greater than 25K Typical Gates and greater than 2K Registers.
Other devices maybe considered upon request.
SX-A A54SX32A, A54SX72A SX A54SX32 MX A42MX24, A42MX36 ProAsic Plus APA075, APA150, APA300, APA450, APA600, APA750, APA1000 Axcelerator AX125, AX250, AX500, AX1000, AX2000 As a bona-fide Actel Customer, when you have the basic information about your design available, and know the possible target Actel device, you may access the resources of the Comit Platform Xpress Program for Actel. Simply go to the Platform Xpress Program Registration and provide us with your contact information and basic information about your design. If you are not sure or need help in selecting the target device, you can still register, and we will help you select your device.
A Comit Customer Service Manager will contact you, and walk you through the program. We will establish an NDA, provide details on the services included and excluded, the design/utilization parameters that must be met and the turn-around time for your design. At this point you are ready to go, and can share the details of your design requirements.
Engineering Report
Based on the information you provide, Comit will prepare a Comit Engineering Report on your project. This will state our understanding of the Design with our assumptions, and cover the following:
- Block Diagram
- Functionality
- Implementation Strategy
- Verification Strategy
- Acceptance Criteria
- Architecture
- Test Plan
- Design
- Test Environment
- Unresolved Issues, if any
- Unknowns and Risks, if any
- Deliverables (see below)
You will be required to sign-off on the Engineering Report. This will form the basis for the Design, and will also form part of Comit Engineering Services Agreement.
Deliverables
This is a general list of deliverables. Exact deliverables may vary and will be listed in the Engineering Report.
- RTL (Verilog default, VHDL if the customer requires it)
- Test Bench
- Test Cases
- Architecture Document including Register
- Interfaces
- Implementation scripts, synplify_pro and Actel Simulation Log Files
- Synthesis Log files (including Timing analysis reports)
- Bitstream for FPGA programming
Services included for the fixed fee are:
- Development of simple bus interfaces
- Integration of Actel IP or 3rd party IP
- Development of clocking, reset strategy
- Suggestions for Board Design (if any)
- Development of models for simple bus interfaces
- Development of Test Cases
- Documentation of software register interfaces and memory map
- Design Report
Services Expressly Excluded for the fixed fee are:
- Development of standard IP:
IPs for standard interfaces, whether commercially available, or not. Examples include but are not limited to:
Ethernet, USB, Processor Cores. Comit and Actel will work together with the customer to identify a third party provider of such IP. Comit's view whether a module required is a standard interface is not is final and binding. Comit may quote to customor for custom development of that module, if required.- Compliance Testing:
Comit will test for many types of transactions, as will be described in the Comit Engineering Report, but full compliance testing is not included as part of the services for the pre-determined fee- Board Bring up
- Board Design, Fab & assembly Services
- Embedded SW Development.
Design/Utilization parameters that must be met, to qualify for the pre-determined Fee:
- Functional Specification must be available in some written form, that clearly describes requirement (minor changes maybe allowed after project start, if mutually agreed)
- Design Qualified as feasible by Actel Representative or Comit Representative
- Proprietary interfaces completely specified,including protocol & timing
- Signals available at project start
- Required IP available, tested and proven in Silicon or Actel Part
- Pinouts available (within 2 weeks of project start, or earlier)
- Logic Modules
utilization:
not to exceed 80% of Total FFs and
not to exceed 70% of Dedicated FFs - Number of Clocks in Design is less than or equal to routed + fixed clocks, in the device
* Program available to bona fide Actel customers only. Program not available to Design Services Companies, Other Design Service Providers, Independent Consultants, FPGA / CPLD manufacturers, their Representatives, and/or distributors.
Program guideleines and offerings may be subject to change without notice.
Your
Design NRE based
on your target Actel device
Device Locked Fee,
based on Actel part #.
Includes Core integration
You get RTL, testbench
sim/synth scripts,
architecture doc,
bitstreamand more
Optional board bringup,
board design and SW
development support
If
you don't yet
have a login ID
please register.
Go
to
The Platform
Xpress
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